1. Field of the Invention
The present invention relates to cell based ASIC designs and particularly to repairing cell based ASIC designs.
2. State of the Art
Customized integrated circuits that perform a specific function, sometimes referred to as ASICs, can be implemented using a gate array (GA). A GA comprises an array of transistors that are uncommitted (i.e. not interconnected) prior to the metalization step of the integrated circuit process. Commonly, the GA is made-up of a plurality of cells--each cell including one or more uncommitted transistors. An ASIC having a particular function can be created by patterning metalization layers to interconnected transistors into a particular circuit configuration so as to cause the gate array to perform the ASIC's specific function. The advantage of GA is its superior fabrication cycle time and ability to accommodate circuit function modifications (repairs to the logic design) rapidly allowing the customer to receive new prototype parts and ramp to high volume production more quickly. The problem with the GA style implementation is that while it provides superior prototype cycle time, it comes at the expense of lower gate density and therefor higher cost. As industry has moved to higher levels of integration with design reuse at the system block level, interest in GA style implementation has been fading.
Instead of using gate arrays, ASICs are now more commonly being implemented with interconnected logic cells (referred to as a cell-based ASIC implementation) instead of an array of transistors. In this type of implementation, each logic cell comprises one or more logic gates such as NAND, NOR gates, invertors, and flip-flops. An ASIC is formed by interconnecting the inputs and outputs of the logic cells with metalization layers to obtain the desired ASIC function. One of the main advantages of a cell-based ASIC implementation is that a library of generic optimized logic cells can be used to design different ASICs and achieve significantly higher gate density which correlates directly to lower product cost and in many cases higher performance.
In cell-based integrated circuit design, metal-only repairs are conventionally performed using repair cells referred to as spare gates which are randomly dispensed throughout the cell-based design. Spare gates generally comprise a collection of transistors coupled together into logic gates which perform a certain function. FIG. 1 shows a typical spare gate logic design which includes a variety of interconnected gates and a D flip-flop. By seeding the layout with this spare gate block when logic changes are required or desired, the spare gate resource can be reconfigured to become part of the customer function. The spare gates can be any of the functions in the cell-based library. The customer can select his own unique combination of gates which he believes may be most useful for repair of his logic function.
One case in which spare gates are used for metal-only functional repairs occurs when fabricating ASIC devices and some wafers are held prior to metal while and the remainder are completed. A functional analysis is performed on the completed devices to determine if they require any simple repairs (i.e., functional modifications) using the spare gates. The remaining wafers which were held prior to metal can then be processed using redesigned metal masks which interconnect spare gates into the ASIC device. This allows for relatively quick metal-only functional fixes without needing to restart wafers from the first step in the process thereby saving several weeks of processing and design time and reducing cost. The problem with the spare gate repair technique is that it is not very flexible. Specifically, when implementing a spare gate in a cell-based design as a repair cell it can only be used to repair/or replace areas needing the same function as the spare gate. As a result, if a certain type of spare gate is unavailable or is unroutable to the repair area then the repair option of metal-only is also unavailable. Consequently, spare gate cell repair presents limitations to the type of functional repairs that are possible in a cell-based implemented integrated circuit.
The present invention is a technique for optimizing metal-only functional repair in a cell-based implemented ASIC.